The present invention relates to the fabrication of semiconductor integrated circuit devices, and more particularly to an efficient method for forming trench-like structures which isolate adjacent p-type and n-type regions of a CMOS integrated circuit. The invention is differentiated by its use of selective epitaxial growth (SEG) with nucleation site control and stress relief.
Conventional integrated circuit semiconductor fabrication practices separate CMOS active regions in a semiconductor substrate with field oxide regions grown from the substrate silicon. Numerous refinements have been proposed and implemented to minimize the deleterious effect of the phenomenon commonly referred to as bird's beak encroachment. Most recently, anisotropic etching and refill technique have been the subject of numerous studies and publications as substitutes for grown field oxide given the present availability of highly directional etching equipment. Unfortunately, the refill by deposition operations have proven to be more intractable than originally anticipated.
It is known that adjacent but differently doped monocrystalline regions can be formed by a selective epitaxial growth/deposition. For example, the article entitled "Selective Epitaxy for CMOS VLSI" by Sabine et al., which appeared in the January 1985 issue of the IEEE Electron Device Letters, describes a selective eptaxial growth (SEG) technique to refill well regions etched in a layer of silicon dioxide which was formed over a substrate. U.S. Pat. No. 4,473,598 describes the filling of trenches with polysilicon or combinations of polycrystalline and epitaxial silicon by selective growth. Other refinements of SEG are described in the article entitled "Advanced Dielectric Isolation Through Selective Epitaxial Growth Techniques" by Borland et al., which appeared in the August 1985 issue of Solid State Technology. The latter article compares and contrasts the various other dielectric isolation technologies in the course of evaluating an SEG technique. Refinements of the SEG concept are further described in the article entitled, "Novel Device Isolation Technology With Selective Epitaxial Growth" by Endo et al., which appeared in the September 1984 issue of the IEEE Transactions On Electron Devices. According to that teaching, the sidewalls of the openings in the oxide layer are coated with a silicon nitride prior to SEG. Other applications of sidewall nitrides with pad/buffer oxides and an anisotropic etching of the silicon substrate are described in the context of an otherwise significantly different process in U.S. Pat. No. 4,604,162.
A very recent publication which bears upon the topic of the present invention is entitled "1/4-um CMOS Isolation Technique Using Selective Epitaxy" by Kasai et al., which appeared in the June 1987 issue of the IEEE Transactions on the Electron Devices. The Kasai et al. technique involves the use of SEG to fill wells formed in substrate recesses, and includes an isolation structure which is trench-like and composed of a very thin nitride layer combined with a relatively thick oxide layer. The formation of undesirable voids in the final isolation structure is an acknowledged defect.